The present inventive concept relates to semiconductor devices, and more particularly, to 1-bit error correction methods and devices capable of quickly finding and correcting an error when the error occurs in a single bit during error correction code (ECC) decoding.
As the data storage and data access bandwidth of semiconductor devices has increased, the incorporation of error correction circuits adapted to the detection and correction of data error(s) has become increasingly common. Data errors are often caused by malfunctioning or defective memory cells. The error correction circuits commonly used in contemporary semiconductor devices include certain error correction circuits using memory cell redundancy and other error correction circuit using ECC capabilities.
A semiconductor memory device including an error correction circuit using memory cell redundancy must provide normal memory cells and redundant memory cells. In operation, this type of semiconductor memory device essentially replaces a defective memory cell with a redundant memory cell during read/write operations. Error correction circuits using redundant memory cells are typically used in dynamic random access memory (DRAM) devices.
Alternately, other semiconductor memory devices including an error correction circuit using ECC capabilities generates and stores parity data (or syndrome data) along with the “payload” data to be stored in memory. Subsequent detection and correction of error(s) in read data obtained from the semiconductor memory device is enabled by the presence of the parity or syndrome data. This type of error correction circuit using ECC capabilities is more commonly associated with read-only memory (ROM) devices, and especially flash memory devices.
Unfortunately, when ECC is used to detect and correct errors in very small quantities of data, the computational overhead and hardware complexity required to provide such capabilities may be unnecessarily (or disproportionately) high. In particular, when a resistance variation (or threshold voltage distribution) does not shift but remains relatively stable within electrically programmable read only memories, including flash memory, the probability of a bit error is typically very low. That is, the likelihood of bit errors (and particularly bit errors exceeding single bit error) occurring in read data obtained from these types of semiconductor memory devices is often insufficient to justify the expense and added complexity required to implement conventional ECC capabilities which are typically ascribed to systems exhibiting a higher incidence of bit errors and particularly multi-bit errors.